Creating VEK280 10G PL Ethernet based Vitis Custom Platform

In this tutorial, we will create a custom Vitis platform that supports 10G PL Ethernet interface through SFP and run a Vector Addition example with that platform. This design targets the VEK280 board.

Required Hardware

• VEK280 Eval Board
• 10G Supported SFP Cable
• SFP+ module
• A host machine or another SFP supported board connected to VEK280 through the cable.

Required Software

• Vivado 2024.1
• Petalinux 2024.1
• VEK280 BSP (xilinx-vek280-v2024.2-11110212.bsp)

To expedite the design process we are beginning with the Versal Extensible Embedded Platform provided in Vivado 2024.1 as our base design and then add the Xilinx 10G/25G AXI Ethernet IP in that design.

First, select the board “Versal VEK280 Evaluation Platform with FMC Connector” and create the project.

The example design will produce a block design as shown below.

For more detailed steps for creating above extensible embedded platform aka minimal platform you could follow the tutorial: https://docs.amd.com/r/en-US/Vitis-Tutorials-Getting-Started/Vitis-Platform

Those mentioned steps are similar to the VCK190 tutorial, with a few modifications. Instead of selecting a part, we have selected a board-based example. Choosing the board automatically applies the appropriate CIPS presets for that specific board, removing the need for manual configuration.

Creating Vitis Platform with 10G PL Ethernet

We are going to use the 10G Ethernet design based on the VCK190 example design provided by the Xilinx, to update in our above example project: https://github.com/Xilinx-Wiki-Projects/Versal-Ethernet/tree/master/VCK190-Ethernet/2023.2/pl_eth_10g

The changes that we need to make in the above VCK190 based 10G pipeline/design are as follows:

• In the Ethernet Subsystem, change the Tx and Rx GT Interface from Channel 2 to Channel 3. The SFP port is connected to the Channel 3 in VEK280 as opposed to Channel 2 in VCK190. This information can be found in the Transceiver Mapping table of VEK280 or from the board schematic.

• Remove the SFP_TX_Disable Constant from the design. In VEK280 SFP_TX_Disable signal is connected through I2C Expander as shown at the schematic (Page 39 - I2C0 expander). We will assert this signal using i2cset tool after we boot the board.You can get the VEK280 schematic here: XTP760 - VEK280 Schematic

The final block design looks like this:

You can also view the block design in pdf format from github.

• Add the following constraints for VEK280:

##### GTY Bank 105 - SFP0 interface pin
set_property PACKAGE_PIN B4 [get_ports {gt_rxp_in_0[3]}]
set_property PACKAGE_PIN B3 [get_ports {gt_rxn_in_0[3]}]
set_property PACKAGE_PIN A7 [get_ports {gt_txp_out_0[3]}]
set_property PACKAGE_PIN A6 [get_ports {gt_txn_out_0[3]}]
### GTREFCLK 0 ( Driven by SI570 )
set_property PACKAGE_PIN H9 [get_ports {CLK_IN_D_clk_p}]
set_property PACKAGE_PIN H8 [get_ports {CLK_IN_D_clk_n}]
####################################################################################
# Timing
####################################################################################
create_clock -period 6.400 -name {CLK_IN_D_clk_p} -waveform {0.000 3.200} [get_ports {CLK_IN_D_clk_p}]

• Make sure correct connections have been enabled in the Platform Setup similar to VCK190 design.
• Validate the design and Generate block design.
• Export the Platform.

Creating Petalinux Boot Components

Since we need i2cset tools which are not enabled in Versal Common Image, we need to make custom rootfs using Petalinux.

Enter the Petalinux directory and execute the following commands:

• Source the Petalinux 2024.1 tool.
• To create Petalinux Project, run the following

petalinux-create -t project -s <PATH-TO-BSP> -n vek280_ethernet

Using BSP is not mandatory but recommended. You can also create the project using basic Versal template.

• Goto project directory

cd vek280_ethernet

• To get xsa

petalinux-config --get-hw-description ../../hardware/xsa/sfp_1g_ethernet_vek280_wrapper.xsa

• In the Petalinux System Configuration make the following changes:

DTG Settings -> MACHINE_NAME -> versal-vek280-revb

Image Packaging Configuration -> Root filesystem type -> EXT4

Exit the System Configuration

• Goto rootfs and make following changes. petalinux-config -c rootfs

Filesystem Packages -> base -> i2c-tools -> [x] i2c-tools

i2c tools are required to toggle SFP_TX_DISABLE signal in VEK280.

Exit the rootfs config.

• Build the project

petalinux-build

• Create BOOT.BIN

petalinux-package boot --format BIN --plm --psmfw --u-boot --dtb -o ./images/linux/BOOT.BIN --force

Custom Vitis Platform Creation

Now we are going to use above petainux generated boot components at building Vitis Platform. After Vitis Platform build then we can add Vector Addition by following the Example.

Follow the Step 2 as mentioned here to build the Vitis Platform using the base platform that we created above : https://docs.amd.com/r/en-US/Vitis-Tutorials-Getting-Started/Step-2-Create-Vitis-Platform

Build the SD Card Image.

You can also open and check the final hardware design of Platform + VADD kernel through this directory:

<Project-Directory>/vadd/build/hw/hw_link/binary_container_1/binary_container_1/vivado/vpl/prj

The final generated hardware platform PL accelerated vector addition is as shown below.

The highlighted block is the Vitis Region added which contains the following IPs:

To validate the design, boot the board with the sd image we just created.

Assert the SFP_TX_DISABLE signal to ‘Low’. To do this will use i2cset command:

sudo i2cset -y 0x20 0x02 0x00

VEK280 10G Etherent Test Setup with VCK190:

Now connect the SFP cable to the Host PC or another 10G SFP supported board. You will see the link is up. You can also check using ip link show command.

Lets set the IP for the eth0 and ping.

Next lets test the PL Accelerated Vector Addition example:

We can see the TEST PASSED in the log.

DPU/NPU integration on Vitis Platform

Coming soon in next tutorial (Part II)...

Also checkout the github link for the full project design scripts and its associated files.

Thanks for going through this tutorial!

A big thank you to Abhidan Jung Thapa (abhidan@logictronix.com) for creating this outstanding and detailed tutorial!

LogicTronix is AMD-Xilinx Partner for FPGA Design and ML Acceleration, for design service, IP cores or Vision Edge AI Solution development you can contact us at info@logictronix.com.